Semiconductor wafers must be tested during the manufacturing process to evaluate the electrical characteristics of the integrated circuits formed on the wafer. Standard tests for gross functionality are typically performed by probe testing the wafers using probe cards and wafer steppers. Other tests such as burn-in, and high speed testing are typically performed after the dice have been singulated and packaged. Among the tests performed are dynamic burn-in, input/output leakage, speed verification, opens, shorts, refresh and a range of algorithms to verify AC parameters.
In the past, burn-in and speed testing have been performed at the die level rather than at the wafer level. One reason that these test procedures are not performed at the wafer level is because the tests require interconnects with a large number of contact members and input/output paths to the wafer. For example, a wafer can include several hundred dice each having twenty or more bond pads. The total number of bond pads on the wafer can be in the thousands. For some tests procedures a contact member and input/output path must be provided to each bond pad. Even with wafer stepping techniques, conventionally formed interconnects, such as probe cards, usually do not include enough contact members (e.g., probes) to test dice having a large number of bond pads.
In addition to contact density limitations, force application and damage to the wafer must be minimized during the wafer testing procedure. In general, a large number of bond pads on the wafer will require that high contact forces be generated between the wafer and interconnect. The high contact forces can damage the wafer, particularly the bond pads that can have a thickness of only 1 .mu.m or less. Damage to thin film metal bond pads can also result from the necessity to penetrate the metal oxide layer on the bond pads to make a good electrical connection.
It would be advantageous for an interconnect to include contact members capable of testing a wafer with a large number of bond pads. This would permit both gross functionality as well as burn-in, dynamic burn-in, and high speed tests to be performed at the wafer level. It would also be advantageous to test all of the dice on the wafer simultaneously so that wafer stepping techniques do not need to be employed. This would decrease the time for testing and improve wafer throughput. Still further, it would be advantageous to be able to control the amount of contact force exerted on the wafer by an interconnect in order to minimize damage to the wafer and bond pads. In view of the foregoing, the present invention is directed to an improved interconnect and method for testing semiconductor wafers.